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CEN/CLC/TR 18202:2025:en
Layer model of Quantum Computing
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This document defines a layer model that covers the entire stack of universal gate-based quantum computers. The group of lower-level (hardware) layers are organized in different hardware stacks tailored to different hardware architectures, while the group of higher-level (software) layers are built on top of these and expected to be common for all quantum computing systems. The higher-up in the stack, the more agnostic it will be from underlying layers. Reducing the dependencies between higher and lower layers is a crucial point for optimized quantum computations. A co-requisite point is to allow for a free but well-defined flow of information up and down the higher and lower layers to allow for co-designing hardware and software.
The scope of this Technical Report is restricted to a universal gate-based quantum-computing model, also known as a digital or circuit quantum-computing model, on multiple physical systems such as transmon, spin-qubit, ion-trap, neutral-atom, and others. This document does not apply to technologies like the universal adiabatic quantum-computing model and its heuristic form quantum annealing, if they do not correspond to a gate-based quantum circuit. Due to major architecture differences in lower layers, it does not apply either to the universal photonic one-way quantum computing model even though it is fully compatible with gate-based quantum-computing model. Moreover, quantum computing models that are not universal, such as quantum simulators and special purposes, are also out of scope.
Limiting the scope to a universal gate-based quantum computing model is justified by expected commonalities at the higher layers, mainly above the hardware abstraction layer (HAL), up to the service layer. These commonalities imply a market for software products usable for this wide range of quantum computing technologies.
The present Technical Report is focussed on a high-level (functional) description of the layers involved. Additional details of the individual layers are reserved for other future CEN/CLC/TRs.
Tämän julkaisun valmistelusta Suomessa vastaa SFS Suomen Standardit, puh. 09 149 9331.
This document defines a layer model that covers the entire stack of universal gate-based quantum computers. The group of lower-level (hardware) layers are organized in different hardware stacks tailored to different hardware architectures, while the group of higher-level (software) layers are built on top of these and expected to be common for all quantum computing systems. The higher-up in the stack, the more agnostic it will be from underlying layers. Reducing the dependencies between higher and lower layers is a crucial point for optimized quantum computations. A co-requisite point is to allow for a free but well-defined flow of information up and down the higher and lower layers to allow for co-designing hardware and software.
The scope of this Technical Report is restricted to a universal gate-based quantum-computing model, also known as a digital or circuit quantum-computing model, on multiple physical systems such as transmon, spin-qubit, ion-trap, neutral-atom, and others. This document does not apply to technologies like the universal adiabatic quantum-computing model and its heuristic form quantum annealing, if they do not correspond to a gate-based quantum circuit. Due to major architecture differences in lower layers, it does not apply either to the universal photonic one-way quantum computing model even though it is fully compatible with gate-based quantum-computing model. Moreover, quantum computing models that are not universal, such as quantum simulators and special purposes, are also out of scope.
Limiting the scope to a universal gate-based quantum computing model is justified by expected commonalities at the higher layers, mainly above the hardware abstraction layer (HAL), up to the service layer. These commonalities imply a market for software products usable for this wide range of quantum computing technologies.
The present Technical Report is focussed on a high-level (functional) description of the layers involved. Additional details of the individual layers are reserved for other future CEN/CLC/TRs.
Tämän julkaisun valmistelusta Suomessa vastaa SFS Suomen Standardit, puh. 09 149 9331.
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12.09.2025
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16.09.2025
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